The invention relates to a method for the computer-aided design of a circuit that contains sections having different supply voltages.
As the scale of integration increases to an ever greater extent and the complexity of the circuits continuously increases, there is a continuous increase in the requirements made of the circuit configuration. Powerful and flexible design tools are required which, at the simulation level, can keep up with the advances in the area of integrated circuit fabrication. This applies both to the verification of the functionality of the circuit and to the accuracy of the prediction of signal time delays in data paths of the circuit.
The computer-aided development of circuits is based on a conceptual circuit concept and contains the steps of the writing-down of the circuit concept in a suitable hardware description language (e.g. VHDL), the analysis of the circuit concept under the aspect of logical functionality, the synthesis of a circuit design (creation of a synthesized net list), the re-analysis of the synthesized design (post-layout analysis) and the programming of a suitable chip fabrication apparatus. The overall process sequence is referred to as xe2x80x9cdesign flowxe2x80x9d.
Difficulties arise if the design tools known heretofore are intended to be used to analyze circuits, which contain sections having different supply voltages. Such multivoltage circuit designs currently have to be analyzed with a high outlay of manual work. First, it is necessary to partition the overall design into sections having different supply voltages. Afterward, it is necessary, likewise by manual work, to insert so-called level shifters at the boundaries of the circuit sections having different supply voltages into the net list. After the creation of the net list, a further serious problem results from the fact that the different supply voltages have to be taken into account in the analysis of the temporal behavior of the designed circuit. This has not been possible heretofore or has only been possible to a very limited extent by so-called xe2x80x9cderatingxe2x80x9d.
It is accordingly an object of the invention to provide a method for designing circuits with sections having different supply voltages which overcome the above-mentioned disadvantages of the prior art methods of this general type, which significantly facilitates the computer-aided design of a circuit with sections having different supply voltages. In particular, the intention is to enable better automation of the synthesis step and more accurate analysis of the temporal behavior of the circuit.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for computer-aided design of a circuit having sections with different supply voltages. The method includes creating a hardware description code of the circuit using logical circuit blocks, allocating a supply voltage to each of the logical circuit blocks, and transforming the hardware description code into a net list containing logical cells and related connections. Each of the logical cells corresponds to a cell type to which is given a unique identifier of the supply voltage to which a logical cell is assigned. An analysis of the circuit is then carried out on a basis of the net list taking account of identifiers of the logical cells.
An essential aspect of the invention is that the logical cells defined in the net list are assigned an identifier that uniquely specifies the supply voltage for which the respective cell is intended to be used. This makes it possible to differentiate cells of identical logical functionality (i.e. of the same cell type) in the net list format, which results in that all further tools in the design sequence, depending on the identifier of the cell, can reference different physical parameters. This will be explained in more detail in connection with the time sequence analysis.
A level shifter cell is preferably incorporated into a connection between two cells with different identifiers.
An advantageous refinement of the invention is characterized in that a connection attribute is assigned to each input and to each output of a logical cell, which connection attribute, in the synthesis of the circuit design (i.e. the transformation of the hardware description code into a net list), has the effect that an output of a first cell can be (directly) connected to an input of a second cell only when the output of the first cell and the input of the second cell have identical connection attributes, and that the allocation of connection attributes for inputs and outputs is effected according to a predetermined assignment specification between the set of identifiers and the set of connection attributes. Therefore, a design rule is established which would be contravened in the case of connection of inputs and outputs with different connection attributes.
A preferred assignment specification consists in a specific identifier of a cell being assigned exactly one connection attribute that is assigned only to the specific identifier. What this achieves is that a direct connection (i.e. one realized without the interposition of a level shifter) between the signal path of adjacent cells is possible only when the cells are assigned to the same supply voltage. An alternative procedure consists in permitting, in specific cases, one and the same connection attribute to be assigned also to different identifiers. This case will be of importance when, with regard to the connection attributes, there is a demand for a differentiation capability that is less fine with regard to different supply voltages than for different identifiers. Since the connection attributes (of the inputs and outputs of the cells) are used in the context of the design synthesis, while the identifiers (of the cells) are used as a basis for the design analysis (and increase the accuracy thereof), this measure may be expedient in many cases.
The definition of connection attributes for inputs and outputs of cells makes it possible for the incorporation of level shifter cells between outputs and inputs with different connection attributes of adjacent cells to be effected automatically in the context of the computer-aided creation of the net list (circuit synthesis). The list significantly reduces the design complexity.
In accordance with an added mode of the invention, during the transforming step, there is performed the step of incorporating automatically a level shifter cell between the output of the first logical cell and the input of the second logical cell, provided that the connection attribute assigned to the output of the first logical cell is not identical to the connection attribute assigned to the input of the second logical cell.
A particularly preferred procedure in the design sequence is characterized in that the analysis step is a time sequence analysis of the circuit.
In this case, it is advantageous if the time sequence analysis contains a calculation step for determining signal transfer times within cells with different identifiers, and, for this purpose, identifier-dependent technology information items with respect to the cells are accessed, the technology information items being contained in a technology cell library. Therefore, it is possible to carry out a time sequence calculation for cells with different identifiers.
One possibility for continuing to perform the time sequence analysis with existing design toolsxe2x80x94which are not specifically designed for the calculation of multivoltage circuitsxe2x80x94consists in providing, after the choice of a reference voltage, a transformation of the identifier-dependent technology information items of the cells as a function of the reference voltage chosen, and then in carrying out the calculation step for cells with different identifiers using the transformed technology information items and the one reference voltage chosen.
In this connection, it is pointed out that the xe2x80x9cidentifier-basedxe2x80x9d form of the time analysis is superior to the known procedure of scaling the input-to-output transfer times by a xe2x80x9cderatingxe2x80x9d factor. This is because xe2x80x9cderatingxe2x80x9d presupposes that the change in the signal transfer time that occurs in the event of a change in the supply voltage can be described according to a predetermined relationship used for the analysis (simply a linear relationship is usually assumed). However, such a predetermined relationship yieldsxe2x80x94at least for a tenable parameterization complexityxe2x80x94a time/voltage behavior that corresponds to reality only in a narrow voltage range, e.g., in the case of linear derating, for instance for voltage fluctuations in the range of +/xe2x88x923% from the desired value. Therefore, multivoltage designs cannot be analyzed satisfactorily in terms of their temporal behavior solely by derating.
In accordance with a further mode of the invention, there is the step of providing identifier-dependent derating parameters in the technology cell library.
In accordance with another mode of the invention, there is the step of calculating a transformed derating parameter of a cell Z according to an equation kn(Z)=(Ubas(Z)/Uref)*k(Z). Where Ubas is the supply voltage assigned to the cell, k(Z) is the transformed derating parameter of the cell Z for the supply voltage and Uref is the reference voltage.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for designing circuits with sections having different supply voltages, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.